Iterative threshold decoding of Convolutional Self-Doubly Orthogonal codes (CSO2C), can provide a very attractive trade-off between hardware implementation complexity, decoding latency and error performances making this error control coding scheme suitable for applications to high speed wireless communication system.
Pipeline Strategies: Two pipeline strategies was developed and applied in order to increase the throughput of the threshold decoder. The Pipeline Capability is introduced as an additional constraint for the search of optimal CSO2C codes characterized by
very high throughput and low complexity at the decoding stage.
Punctured CSO2C Codes: In order to implement the punctured encoder and the corresponding decoder, a Puncture Module and an Insert Erasure Module as well as an elaborate Clock Manager module was developed and integrated in the communication system. All of these modules support compatible-rates codes.
Prototyping and Experimental Results: The communication system was prototyped using the ARM Integrator platform. The décoder throughput reached 265 Mbps for Single Shift Register Codes and 1 Gbps for 5-Shift Registers Codes.
